TOE1G-IP core for FPGA
TCP/IP communication functionality can be implemented with pure hardware logic without a CPU!
The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes with a reference design compatible with Xilinx/Altera FPGAs as a standard attachment to the core product, which can help shorten product development time.
- 企業:デザイン・ゲートウェイ
- 価格:Other